Integrated circuits (IC's) typically include a large number of components, particularly transistors. One type of transistor is a metal-oxide-semiconductor field-effect-transistor (MOSFET). MOSFET devices typically include a gate structure on top of a semiconductor substrate. Both sides of the gate structure are doped to form source and drain regions. A channel is formed between the source and drain regions beneath the gate. Based on a voltage bias applied to the gate, electric current may either be allowed to flow through the channel or be inhibited from doing so.
In some cases, the channel may be formed as a fin-like structure (herein “fin”). Such a fin protrudes beyond a top surface of the substrate and runs perpendicular to the gate structure formed on the substrate and the fin. In general, a field-effect-transistor using such a fin as a channel is referred to as a fin field-effect-transistor (“FinFET”). A conventional replacement gate process is typically used to make the gate feature of such a FinFET. The conventional replacement gate process typically includes forming a dummy gate over a central portion of the fin, voiding the dummy gate, refilling such a void with a gate dielectric layer (e.g., a high-k dielectric material), and subsequently overlaying the gate dielectric layer with at least one conductive material (e.g., a metal material) so as to form a metal gate feature that includes the gate dielectric layer and the conductive material over the central portion of the fin, which is the channel of the FinFET.
In particular, the dummy gate typically has two substantially vertical sidewalls, wherein each sidewall is formed as a single continuous surface, which causes the void to have respective sidewalls that are each a continuous surface extending from respective bottom to top. As such, when refilling the void with the gate dielectric layer and subsequently with the at least one conductive material, due to the single continuous sidewall of the void, the conductive material cannot surround the fin channel thoroughly, especially at end portions of the fin channel. This can disadvantageously cause various issues such as, for example, a poor gate controllability of the FinFET, a severer drain-induced barrier lowering (DIBL) effect, etc. Thus, conventional FinFET's gate features and techniques to form the same are not entirely satisfactory.